logic_core.rtl Architecture Reference

Architecture >> logic_core::rtl

Components
a_input_register	<Entity a_input_register>
b_input_register	<Entity b_input_register>
mos_6502_alu	<Entity mos_6502_alu>
adder_hold_register	<Entity adder_hold_register>

Signals
a_input_data	std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
b_input_data	std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
alu_output	std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Instantiations
ai0	a_input_register <Entity a_input_register>
bi0	b_input_register <Entity b_input_register>
alu0	mos_6502_alu <Entity mos_6502_alu>
add0	adder_hold_register <Entity adder_hold_register>

Member Data Documentation

a_input_data

a_input_data std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

a_input_register

a_input_register

Component

add0

add0 adder_hold_register

Instantiation

adder_hold_register

adder_hold_register

Component

ai0

ai0 a_input_register

Instantiation

alu0

alu0 mos_6502_alu

Instantiation

alu_output

alu_output std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

b_input_data

b_input_data std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

b_input_register

b_input_register

Component

bi0

bi0 b_input_register

Instantiation

mos_6502_alu

mos_6502_alu

Component

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/alu/core.vhdl