mos_6502_alu Entity Reference

Inheritance diagram for mos_6502_alu:

Entities
mos_6502_alu.rtl	architecture

Ports
a	in	std_ulogic_vector ( 7 downto 0 )
		The A input register for the ALU.
b	in	std_ulogic_vector ( 7 downto 0 )
		The B input register for the ALU.
result	out	std_ulogic_vector ( 7 downto 0 )
		The output word from the ALU.
carry_out_ACR	out	std_ulogic
overflow_AVR	out	std_ulogic
half_carry_HC	out	std_ulogic
decimal_enable_DAA	in	std_ulogic
carry_in_IADDC	in	std_ulogic
enable_sum_SUMS	in	std_ulogic
enable_and_ANDS	in	std_ulogic
enable_xor_EORS	in	std_ulogic
enable_or_ORS	in	std_ulogic
enable_right_shift_SRS	in	std_ulogic

Member Data Documentation

a

a in std_ulogic_vector ( 7 downto 0 )

Port

The A input register for the ALU.

b

b in std_ulogic_vector ( 7 downto 0 )

Port

The B input register for the ALU.

carry_in_IADDC

carry_in_IADDC in std_ulogic

Port

Carry-in input port for the ALU I/ADDC - ALU Carry-in Input

carry_out_ACR

carry_out_ACR out std_ulogic

Port

ACR - An output flag that is true if the result is > 255 ACR - ALU Carryout

decimal_enable_DAA

decimal_enable_DAA in std_ulogic

Port

Controls whether the ALU is in normal mode or BCD mode DAA - ALU Decimal Mode Enable

enable_and_ANDS

enable_and_ANDS in std_ulogic

Port

Enable logical AND ANDS - ALU Logical AND Enable

enable_or_ORS

enable_or_ORS in std_ulogic

Port

Enable logical OR ORS - ALU Logical OR Enable

enable_right_shift_SRS

enable_right_shift_SRS in std_ulogic

Port

Enable right shift SRS - ALU Shift Right Enable

enable_sum_SUMS

enable_sum_SUMS in std_ulogic

Port

Enable summing the inputs SUMS - ALU Summation Enable

enable_xor_EORS

enable_xor_EORS in std_ulogic

Port

Enable logical XOR EORS - ALU Logical XOR Enable

half_carry_HC

half_carry_HC out std_ulogic

Port

HC - An output flag of unknown purpose HC - ALU Half Carry ??

overflow_AVR

overflow_AVR out std_ulogic

Port

AVR - An output flag that is set when the signed result of an operation overflows. AVR - ALU Overflow

result

result out std_ulogic_vector ( 7 downto 0 )

Port

The output word from the ALU.

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/alu/alu.vhdl