a_input_register Entity Reference

Inheritance diagram for a_input_register:

Entities
a_input_register.rtl	architecture

Ports
load_SB_ADD	in	std_ulogic
		SB/ADD - Load from the SB bus into the A input register
data_in_SB	in	std_ulogic_vector ( 7 downto 0 )
		Data input via the SB bus.
clear_0_ADD	in	std_ulogic
		0/ADD - Load 0s into the A input register
data_out	out	std_ulogic_vector ( 7 downto 0 )
		Data output into the ALU.
metaclock	in	std_ulogic

Member Data Documentation

clear_0_ADD

clear_0_ADD in std_ulogic

Port

0/ADD - Load 0s into the A input register

data_in_SB

data_in_SB in std_ulogic_vector ( 7 downto 0 )

Port

Data input via the SB bus.

data_out

data_out out std_ulogic_vector ( 7 downto 0 )

Port

Data output into the ALU.

load_SB_ADD

load_SB_ADD in std_ulogic

Port

SB/ADD - Load from the SB bus into the A input register

metaclock

metaclock in std_ulogic

Port

Clock to drive the latch circuitry Metaclock

---

The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/alu/a_input_register.vhdl