b_input_register Entity Reference

Inheritance diagram for b_input_register:

Entities
b_input_register.rtl	architecture

Ports
control_not_db_add	in	std_ulogic
control_db_add	in	std_ulogic
control_adl_add	in	std_ulogic
data_in_db	in	std_ulogic_vector ( 7 downto 0 )
		The DB bus port.
data_in_adl	in	std_ulogic_vector ( 7 downto 0 )
		The ADL bus port.
data_out	out	std_ulogic_vector ( 7 downto 0 )
		The output port.
metaclock	in	std_ulogic

Member Data Documentation

control_adl_add

control_adl_add in std_ulogic

Port

Load a word from the ADL bus ADL/ADD ALU B Register Load ADL Bus

control_db_add

control_db_add in std_ulogic

Port

Load a word from the DB bus DB/ADD ALU B Register Load

control_not_db_add

control_not_db_add in std_ulogic

Port

Load an inverted word from the DB bus NOT(DB)/ADD ALU B Register Load Inverted

data_in_adl

data_in_adl in std_ulogic_vector ( 7 downto 0 )

Port

The ADL bus port.

data_in_db

data_in_db in std_ulogic_vector ( 7 downto 0 )

Port

The DB bus port.

data_out

data_out out std_ulogic_vector ( 7 downto 0 )

Port

The output port.

metaclock

metaclock in std_ulogic

Port

Metaclock Metaclock

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/alu/b_input_register.vhdl