adder_hold_register Entity Reference

Inheritance diagram for adder_hold_register:

Entities
adder_hold_register.rtl	architecture

Ports
load		std_ulogic
data_in		std_ulogic_vector ( 7 downto 0 )
		The data to be loaded into the register.
sb_bus_enable_ADD_SB_0_6	in	std_ulogic
		ADD/SB(0-6) - Enable Adder Hold Register SB Bus Outpu, bits 0-6
sb_bus_enable_ADD_SB_7	in	std_ulogic
		ADD/SB(7) - Enable Adder Hold Register SB Bus Outpu, bit 7
sb_bus_port	out	std_ulogic_vector ( 7 downto 0 )
		Port for the SB bus of the MOS 6502.
adl_bus_enable_ADD_ADL	in	std_ulogic
		ADD/ADL - Enable Adder Hold Register ADL Bus Output
adl_bus_port	out	std_ulogic_vector ( 7 downto 0 )
		Port for the ADL bus of the MOS 6502.

Member Data Documentation

adl_bus_enable_ADD_ADL

adl_bus_enable_ADD_ADL in std_ulogic

Port

ADD/ADL - Enable Adder Hold Register ADL Bus Output

adl_bus_port

adl_bus_port out std_ulogic_vector ( 7 downto 0 )

Port

Port for the ADL bus of the MOS 6502.

data_in

data_in std_ulogic_vector ( 7 downto 0 )

Port

The data to be loaded into the register.

load

load std_ulogic

Port

Load signal for the register from the data input Should be wired to the clock generator Phi2 output

sb_bus_enable_ADD_SB_0_6

sb_bus_enable_ADD_SB_0_6 in std_ulogic

Port

ADD/SB(0-6) - Enable Adder Hold Register SB Bus Outpu, bits 0-6

sb_bus_enable_ADD_SB_7

sb_bus_enable_ADD_SB_7 in std_ulogic

Port

ADD/SB(7) - Enable Adder Hold Register SB Bus Outpu, bit 7

sb_bus_port

sb_bus_port out std_ulogic_vector ( 7 downto 0 )

Port

Port for the SB bus of the MOS 6502.

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/alu/adder_hold_register.vhdl