nesgate
VHDL emulation of the Nintendo Entertainment System
 
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Ports
status_register Entity Reference
Inheritance diagram for status_register:
mos_6502_datapath

Entities

status_register.rtl  architecture
 

Ports

db_bus   inout   std_ulogic_vector ( 7 downto 0 )
  The DB bus
enable_P_DB   in   std_ulogic
  Ricoh_2A03_Signal_P_DB
signal_IR5   in   std_ulogic
  Ricoh_2A03_Signal_IR5
signal_ACR   in   std_ulogic
  ACR - ALU Carryout
signal_AVR   in   std_ulogic
  AVR - ALU Overflow
signal_DB0_C   in   std_ulogic
  DB0/C Set C to the value of DB(0)
signal_IR5_C   in   std_ulogic
  IR5/C Set C to the value of IR5 bit
signal_ACR_C   in   std_ulogic
  ACR/C Set C to the value of ACR
signal_DB1_Z   in   std_ulogic
  DB1/Z Set Z to the value of DB(1)
signal_DBZ_Z   in   std_ulogic
  DBZ/Z Set Z to the value of DBZ
signal_DB2_I   in   std_ulogic
  DB2/I Set I to the value of DB(2)
signal_IR5_I   in   std_ulogic
  IR5/I Set I to the value of IR5
signal_DB3_D   in   std_ulogic
  DB3/D Set D to the value of DB(3)
signal_IR5_D   in   std_ulogic
  IR5/D Set D to the value of IR5
signal_DB6_V   in   std_ulogic
  DB6/V Set V to the value of DB(6)
signal_AVR_V   in   std_ulogic
  AVR/V Set V to the value of AVR
signal_1_V   in   std_ulogic
  1/V Set V to the value of 1/V
signal_DB7_N   in   std_ulogic
  DB7/N Set N to the value of DB(7)

Detailed Description

Processor status register (P) for the 6502 The Processor Status Register (P)

Member Data Documentation

◆ db_bus

db_bus inout std_ulogic_vector ( 7 downto 0 )
Port

The DB bus

◆ enable_P_DB

enable_P_DB in std_ulogic
Port

Ricoh_2A03_Signal_P_DB

◆ signal_1_V

signal_1_V in std_ulogic
Port

1/V Set V to the value of 1/V

◆ signal_ACR

signal_ACR in std_ulogic
Port

ACR - ALU Carryout

◆ signal_ACR_C

signal_ACR_C in std_ulogic
Port

ACR/C Set C to the value of ACR

◆ signal_AVR

signal_AVR in std_ulogic
Port

AVR - ALU Overflow

◆ signal_AVR_V

signal_AVR_V in std_ulogic
Port

AVR/V Set V to the value of AVR

◆ signal_DB0_C

signal_DB0_C in std_ulogic
Port

DB0/C Set C to the value of DB(0)

◆ signal_DB1_Z

signal_DB1_Z in std_ulogic
Port

DB1/Z Set Z to the value of DB(1)

◆ signal_DB2_I

signal_DB2_I in std_ulogic
Port

DB2/I Set I to the value of DB(2)

◆ signal_DB3_D

signal_DB3_D in std_ulogic
Port

DB3/D Set D to the value of DB(3)

◆ signal_DB6_V

signal_DB6_V in std_ulogic
Port

DB6/V Set V to the value of DB(6)

◆ signal_DB7_N

signal_DB7_N in std_ulogic
Port

DB7/N Set N to the value of DB(7)

◆ signal_DBZ_Z

signal_DBZ_Z in std_ulogic
Port

DBZ/Z Set Z to the value of DBZ

◆ signal_IR5

signal_IR5 in std_ulogic
Port

Ricoh_2A03_Signal_IR5

◆ signal_IR5_C

signal_IR5_C in std_ulogic
Port

IR5/C Set C to the value of IR5 bit

◆ signal_IR5_D

signal_IR5_D in std_ulogic
Port

IR5/D Set D to the value of IR5

◆ signal_IR5_I

signal_IR5_I in std_ulogic
Port

IR5/I Set I to the value of IR5

The documentation for this design unit was generated from the following file: