The circuitry of the 6502 is controlled by 62 signals from the instruction decoder, which enables and disables various parts of the CPU at different phases of execution. They are presented here in linear order as depicted by Dr. Hansen's block diagram, and the index of each signal in this list corresponds to the index of that signal in the control_signals inputs that are commonly used by the project

Data latch control signals

<tt>DL/DB</tt> Data Input Latch DB Bus Output Enable

<tt>DL/ADL</tt> Data Input Latch ADL Bus Output Enable

<tt>DL/ADH</tt> Data Input Latch ADH Bus Output Enable

Uncategorized

<tt>0/ADH0</tt>

<tt>0/ADH(1-7)</tt>

<tt>ADH/ABH</tt>

<tt>ADL/ABL</tt>

<tt>PCL/PCL</tt>

<tt>ADL/PCL</tt>

<tt>I/PC</tt>

<tt>PCL/DB</tt>

<tt>PCL/ADL</tt>

<tt>PCH/PCH</tt>

<tt>ADH/PCH</tt>

<tt>PCH/DB</tt>

<tt>PCH/ADH</tt>

<tt>SB/ADH</tt>

<tt>SB/DB</tt>

<tt>0/ADL0</tt>

<tt>0/ADL1</tt>

<tt>0/ADL2</tt>

Stack pointer signals

<tt>S/ADL</tt> Enable S register output to ADL bus

<tt>SB/S</tt> Load value into S register from SB bus

<tt>S/S</tt> Refresh S register value

Note - this signal is not implemented by this core. It appears to be necessary for the actual register, as-implemented, to keep it's value valid between many CPU cycles (since it might be a long time between reads/writes), but that is not necessary on FPGA fabric.

<tt>S/SB</tt> Enable S register output to the SB bus

ALU Signals

<tt>NOT(DB)/ADD</tt> ALU B Register Load Inverted

Load the inverse of a word from the DB bus into the B input register of the ALU

<tt>DB/ADD</tt> ALU B Register Load

Load a word from the DB bus into the B input register of the ALU

<tt>ADL/ADD</tt> ALU B Register Load ADL Bus

Load a word from the ADL bus into the B input register of the ALU

<tt>I/ADDC</tt> - ALU Carry-in Input

Control line for carry-in

<tt>DAA</tt> - ALU Decimal Mode Enable

This controls whether the ALU operates in normal mode or in BCD

<tt>DSA</tt> - ALU

Unknown, related to BCD correction

<tt>SUMS</tt> - ALU Summation Enable

<tt>ANDS</tt> - ALU Logical AND Enable

<tt>EORS</tt> - ALU Logical XOR Enable

At least, exclusive is what I'm guessing the "E" in "EOR" expands to.

<tt>ORS</tt> - ALU Logical OR Enable

<tt>SRS</tt> - ALU Shift Right Enable

TBD: Is this a logical or arithmetic shift?

The 6502 supports instructions for both, and strangely while this only seems to support right-shifts I know the CPU also has both arithmetic and logical left shifts.

<tt>ADD/ADL</tt> - Enable Adder Hold Register ADL Bus Output

<tt>ADD/SB(0-6)</tt> - Enable Adder Hold Register SB Bus Outpu, bits 0-6

<tt>ADD/SB(7)</tt> - Enable Adder Hold Register SB Bus Outpu, bit 7

<tt>0/ADD</tt> - Load 0s into the A input register

<tt>SB/ADD</tt> - Load from the SB bus into the A input register

Register control signals

<tt>SB/AC</tt> - Load from SB bus into the accumulator

This is nominally routed through the BCD correction circuity, but this core doesn't yet implement that, so the routing is direct.

<tt>AC/DB</tt> - Enable Accumulator output to DB bus

<tt>AC/SB</tt> - Enable Accumulator output to SB bus

<tt>SB/X</tt>

<tt>X/SB</tt>

<tt>SB/Y</tt>

<tt>Y/SB</tt>

Processor Status Register Signals

<tt>P/DB</tt> Enable DB bus output for P register

<tt>DB0/C</tt> Set C to the value of DB(0)

<tt>IR5/C</tt> Set C to the value of IR5 bit

<tt>ACR/C</tt> Set C to the value of ACR

<tt>DB1/Z</tt> Set Z to the value of DB(1)

<tt>DBZ/Z</tt> Set Z to the value of DBZ

<tt>DB2/I</tt> Set I to the value of DB(2)

<tt>IR5/I</tt> Set I to the value of IR5

<tt>DB3/D</tt> Set D to the value of DB(3)

<tt>IR5/D</tt> Set D to the value of IR5

<tt>DB6/V</tt> Set V to the value of DB(6)

<tt>AVR/V</tt> Set V to the value of AVR

<tt>1/V</tt> Set V to the value of 1/V

Todo: There's a related signal 0/V that isn't always labelled... does this need implementation?

<tt>DB7/N</tt> Set N to the value of DB(7)

External CPU Signals

<tt>R/NOT W</tt> Read/write signal

When asserted, the CPU wants to execute a bus read on the next Phi2. Conversely, when not asserted, the CPU wants to execute a write on the next Phi2.