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VHDL emulation of the Nintendo Entertainment System
 
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Processes | Signals
status_register.rtl Architecture Reference
Architecture >> status_register::rtl

Processes

PROCESS_16  ( signal_DB0_C , signal_IR5_C , signal_ACR_C , db_bus ( 0 ) , signal_ACR , signal_IR5 )
PROCESS_17  ( signal_DB1_Z , signal_DBZ_Z , db_bus ( 1 ) , DBZ )
PROCESS_18  ( signal_DB2_I , signal_IR5_I , db_bus ( 2 ) , signal_IR5 )
PROCESS_19  ( signal_DB3_D , signal_IR5_D , db_bus ( 3 ) , signal_IR5 )
PROCESS_20  ( signal_DB6_V , signal_AVR_V , signal_1_V , db_bus ( 6 ) , signal_AVR , signal_1_V )
PROCESS_21  ( signal_DB7_N , db_bus ( 7 ) )

Signals

DBZ  std_ulogic
register_data  std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Member Function/Procedure/Process Documentation

◆ PROCESS_16()

PROCESS_16 (   signal_DB0_C ,
  signal_IR5_C ,
  signal_ACR_C ,
  db_bus ( 0 ) ,
  signal_ACR ,
  signal_IR5  
)
Process

◆ PROCESS_17()

PROCESS_17 (   signal_DB1_Z ,
  signal_DBZ_Z ,
  db_bus ( 1 ) ,
  DBZ  
)
Process

◆ PROCESS_18()

PROCESS_18 (   signal_DB2_I ,
  signal_IR5_I ,
  db_bus ( 2 ) ,
  signal_IR5  
)
Process

◆ PROCESS_19()

PROCESS_19 (   signal_DB3_D ,
  signal_IR5_D ,
  db_bus ( 3 ) ,
  signal_IR5  
)
Process

◆ PROCESS_20()

PROCESS_20 (   signal_DB6_V ,
  signal_AVR_V ,
  signal_1_V ,
  db_bus ( 6 ) ,
  signal_AVR ,
  signal_1_V  
)
Process

◆ PROCESS_21()

PROCESS_21 (   signal_DB7_N ,
  db_bus ( 7 )  
)
Process

Member Data Documentation

◆ DBZ

DBZ std_ulogic
Signal

◆ register_data

register_data std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
Signal
The documentation for this design unit was generated from the following file: