mos_6502_datapath Entity Reference

Inheritance diagram for mos_6502_datapath:

Entities
mos_6502_datapath.rtl	architecture

Ports
data	inout	std_ulogic_vector ( 7 downto 0 )
		The external-facing data pins.
address	inout	std_ulogic_vector ( 15 downto 0 )
		The external-facing address pins.
phi1	in	std_ulogic
		Ricoh_2A03_PHI1
phi2	in	std_ulogic
		Ricoh_2A03_PHI2
databus_SB	inout	std_ulogic_vector ( 7 downto 0 )
		The SB bus
databus_DB	out	std_ulogic_vector ( 7 downto 0 )
		The DB bus
databus_ADH	out	std_ulogic_vector ( 7 downto 0 )
		The ADH bus
databus_ADL	out	std_ulogic_vector ( 7 downto 0 )
		The ADL bus
load_SB_AC	in	std_ulogic
		SB/AC - Load from SB bus into the accumulator
output_enable_AC_SB	in	std_ulogic
		AC/SB - Enable Accumulator output to SB bus
output_enable_AC_DB	in	std_ulogic
		AC/DB - Enable Accumulator output to DB bus

Detailed Description

Wrapper component holding the data input/output latches, the index registers, the address registers, and the status register. TODO: Add precharge and drain MOSFETs

Member Data Documentation

address

address inout std_ulogic_vector ( 15 downto 0 )

Port

The external-facing address pins.

data

data inout std_ulogic_vector ( 7 downto 0 )

Port

The external-facing data pins.

databus_ADH

databus_ADH out std_ulogic_vector ( 7 downto 0 )

Port

The ADH bus

databus_ADL

databus_ADL out std_ulogic_vector ( 7 downto 0 )

Port

The ADL bus

databus_DB

databus_DB out std_ulogic_vector ( 7 downto 0 )

Port

The DB bus

databus_SB

databus_SB inout std_ulogic_vector ( 7 downto 0 )

Port

The SB bus

load_SB_AC

load_SB_AC in std_ulogic

Port

SB/AC - Load from SB bus into the accumulator

output_enable_AC_DB

output_enable_AC_DB in std_ulogic

Port

AC/DB - Enable Accumulator output to DB bus

output_enable_AC_SB

output_enable_AC_SB in std_ulogic

Port

AC/SB - Enable Accumulator output to SB bus

phi1

phi1 in std_ulogic

Port

Ricoh_2A03_PHI1

phi2

phi2 in std_ulogic

Port

Ricoh_2A03_PHI2

---

The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/datapath/core.vhdl