mos_6502_alu.rtl Architecture Reference

Architecture >> mos_6502_alu::rtl

Signals
a_register_extended	std_ulogic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
b_register_extended	std_ulogic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
sum_register	std_ulogic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )

Member Data Documentation

a_register_extended

a_register_extended std_ulogic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )

Signal

b_register_extended

b_register_extended std_ulogic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )

Signal

sum_register

sum_register std_ulogic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/alu/alu.vhdl