data_output_latch Entity Reference

Inheritance diagram for data_output_latch:

Entities
data_output_latch.rtl	architecture

Ports
phi1	in	std_ulogic
		Phi1
phi2	in	std_ulogic
		Phi2
signal_R_NOT_W	in	std_ulogic
		R/NOT W Read/write signal
data_in	in	std_ulogic_vector ( 7 downto 0 )
data_out	out	std_ulogic_vector ( 7 downto 0 )
		Data output, connected to the D0-D7 pins.

Member Data Documentation

data_in

data_in in std_ulogic_vector ( 7 downto 0 )

Port

Data input, connected to the DB bus The DB bus

data_out

data_out out std_ulogic_vector ( 7 downto 0 )

Port

Data output, connected to the D0-D7 pins.

phi1

phi1 in std_ulogic

Port

Phi1

phi2

phi2 in std_ulogic

Port

Phi2

signal_R_NOT_W

signal_R_NOT_W in std_ulogic

Port

R/NOT W Read/write signal

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/datapath/data_output_latch.vhdl