data_output_latch.rtl Architecture Reference

Architecture >> data_output_latch::rtl

Processes
PROCESS_9	( phi1 , data_in )
PROCESS_10	( phi2 )

Signals
register_data	std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Member Function/Procedure/Process Documentation

PROCESS_10()

PROCESS_10 (   phi2   )

Process

PROCESS_9()

PROCESS_9 (   phi1 ,   data_in   )

Process

Member Data Documentation

register_data

register_data std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/datapath/data_output_latch.vhdl