data_input_latch Entity Reference

Data input latch for the Ricoh 2A03, connected to the DB, ADL, and ADH buses. More...

Inheritance diagram for data_input_latch:

Entities
data_input_latch.rtl	architecture

Ports
load	in	std_ulogic
data_in	in	std_ulogic_vector ( 7 downto 0 )
		The data to be loaded into the register, maps to D0-D7.
db_bus_enable_DL_DB	in	std_ulogic
		DL/DB Data Input Latch DB Bus Output Enable
db_bus_port	out	std_ulogic_vector ( 7 downto 0 )
		The DB bus
adh_bus_enable_DL_ADH	in	std_ulogic
		DL/ADH Data Input Latch ADH Bus Output Enable
adh_bus_port	out	std_ulogic_vector ( 7 downto 0 )
		The ADH bus
adl_bus_enable_DL_ADL	in	std_ulogic
		DL/ADL Data Input Latch ADL Bus Output Enable
adl_bus_port	out	std_ulogic_vector ( 7 downto 0 )
		The ADL bus

Detailed Description

Data input latch for the Ricoh 2A03, connected to the DB, ADL, and ADH buses.

Member Data Documentation

adh_bus_enable_DL_ADH

adh_bus_enable_DL_ADH in std_ulogic

Port

DL/ADH Data Input Latch ADH Bus Output Enable

adh_bus_port

adh_bus_port out std_ulogic_vector ( 7 downto 0 )

Port

The ADH bus

adl_bus_enable_DL_ADL

adl_bus_enable_DL_ADL in std_ulogic

Port

DL/ADL Data Input Latch ADL Bus Output Enable

adl_bus_port

adl_bus_port out std_ulogic_vector ( 7 downto 0 )

Port

The ADL bus

data_in

data_in in std_ulogic_vector ( 7 downto 0 )

Port

The data to be loaded into the register, maps to D0-D7.

db_bus_enable_DL_DB

db_bus_enable_DL_DB in std_ulogic

Port

DL/DB Data Input Latch DB Bus Output Enable

db_bus_port

db_bus_port out std_ulogic_vector ( 7 downto 0 )

Port

The DB bus

load

load in std_ulogic

Port

Load signal for the register from the data input Should be wired to the clock generator Phi2 output

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/datapath/data_input_latch.vhdl