data_input_latch.rtl Architecture Reference

Architecture >> data_input_latch::rtl

Processes
PROCESS_8	( load , data_in )

Signals
register_data	std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Member Function/Procedure/Process Documentation

PROCESS_8()

PROCESS_8 (   load ,   data_in   )

Process

Member Data Documentation

register_data

register_data std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/datapath/data_input_latch.vhdl