clock_divider.rtl Architecture Reference

Architecture >> clock_divider::rtl

Processes
PROCESS_2	( clk )

Signals
counter	natural range 0 to divide_by - 1 := 0
output_value	std_ulogic := ' 0 '

Member Function/Procedure/Process Documentation

PROCESS_2()

PROCESS_2 (   clk   )

Process

Member Data Documentation

counter

counter natural range 0 to divide_by - 1 := 0

Signal

output_value

output_value std_ulogic := ' 0 '

Signal

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The documentation for this design unit was generated from the following file:

• cores/clock_divider/clock_divider.vhdl