clock_divider Entity Reference

A simple clock divider that takes an input clock and outputs a slower clock signal where each rising edge of the output clock happens after divide_by rising edges from the input clock, and the output is held high for another divide_by rising edges of the input clock. More...

Inheritance diagram for clock_divider:

Generics
divide_by	natural := 2
	How many times to divid.

Ports
clk	in	std_ulogic
clk_out	out	std_ulogic := ' 0 '

Detailed Description

A simple clock divider that takes an input clock and outputs a slower clock signal where each rising edge of the output clock happens after divide_by rising edges from the input clock, and the output is held high for another divide_by rising edges of the input clock.

Template Parameters

divide_by

The number of times to divide the input clock by

Parameters

[in]	clk	The input clock to divide by
[out]	clk_out	The divided clock signal

Member Data Documentation

clk

clk in std_ulogic

Port

clk_out

clk_out out std_ulogic := ' 0 '

Port

divide_by

divide_by natural := 2

Generic

How many times to divid.

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The documentation for this design unit was generated from the following file:

• cores/clock_divider/clock_divider.vhdl