b_input_register.rtl Architecture Reference

Architecture >> b_input_register::rtl

Processes
PROCESS_6	( metaclock )

Signals
data_latch	std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Member Function/Procedure/Process Documentation

PROCESS_6()

PROCESS_6 (   metaclock   )

Process

Member Data Documentation

data_latch

data_latch std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/alu/b_input_register.vhdl