stack_pointer Entity Reference

Entities
stack_pointer.rtl	architecture

Ports
signal_S_SB	in	std_ulogic
		S/SB Enable S register output to the SB bus
signal_S_ADL	in	std_ulogic
		S/ADL Enable S register output to ADL bus
signal_SB_S	in	std_ulogic
		SB/S Load value into S register from SB bus
bus_SB	inout	std_logic_vector ( 7 downto 0 )
		The SB bus
bus_ADL	out	std_logic_vector ( 7 downto 0 )
		The ADL bus

Member Data Documentation

bus_ADL

bus_ADL out std_logic_vector ( 7 downto 0 )

Port

The ADL bus

bus_SB

bus_SB inout std_logic_vector ( 7 downto 0 )

Port

The SB bus

signal_S_ADL

signal_S_ADL in std_ulogic

Port

S/ADL Enable S register output to ADL bus

signal_S_SB

signal_S_SB in std_ulogic

Port

S/SB Enable S register output to the SB bus

signal_SB_S

signal_SB_S in std_ulogic

Port

SB/S Load value into S register from SB bus

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/datapath/stack_pointer.vhdl