nesgate
VHDL emulation of the Nintendo Entertainment System
 
Loading...
Searching...
No Matches
program_counter_low.rtl Architecture Reference

RTL architecture of the program counter low register. More...

Architecture >> program_counter_low::rtl

Processes

PROCESS_12  ( signal_PCL_PCL , signal_ADL_PCL , program_counter_register , bus_ADL )
PROCESS_13  ( program_counter_select_register , signal_1_PC )
PROCESS_14  ( phi2 )

Signals

program_counter_register  std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
increment_register  std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
program_counter_select_register  std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Detailed Description

RTL architecture of the program counter low register.

Member Function/Procedure/Process Documentation

◆ PROCESS_12()

PROCESS_12 (   signal_PCL_PCL ,
  signal_ADL_PCL ,
  program_counter_register ,
  bus_ADL  
)
Process

◆ PROCESS_13()

PROCESS_13 (   program_counter_select_register ,
  signal_1_PC  
)
Process

◆ PROCESS_14()

PROCESS_14 (   phi2  
)
Process

Member Data Documentation

◆ increment_register

increment_register std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ program_counter_register

program_counter_register std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ program_counter_select_register

program_counter_select_register std_ulogic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
Signal

The documentation for this design unit was generated from the following file: