program_counter_low Entity Reference

Program Counter Low register entity. More...

Entities
program_counter_low.rtl	architecture
	RTL architecture of the program counter low register. More...

Ports
phi2	in	std_ulogic
		Clock_PHI2 System clock signal
signal_PCL_DB	in	std_ulogic
		Signal_PCL_DB Program counter low value to data bus
signal_PCL_ADL	in	std_ulogic
		Signal_PCL_ADL Program counter low value to address low bus
signal_1_PC	in	std_ulogic
		Signal_1_PC Increment program counter
signal_PCL_PCL	in	std_ulogic
		Signal_PCL_PCL Store program counter low value
signal_ADL_PCL	in	std_ulogic
		Signal_ADL_PCL Load PCL from address low bus
signal_PCLC	out	std_ulogic
		Signal_PCLC Program counter low carry output
bus_ADL	inout	std_ulogic_vector ( 7 downto 0 )
		Bus_ADL Address low bus
bus_DB	inout	std_ulogic_vector ( 7 downto 0 )
		Bus_DB Data bus

Detailed Description

Program Counter Low register entity.

Member Data Documentation

bus_ADL

bus_ADL inout std_ulogic_vector ( 7 downto 0 )

Port

Bus_ADL Address low bus

bus_DB

bus_DB inout std_ulogic_vector ( 7 downto 0 )

Port

Bus_DB Data bus

phi2

phi2 in std_ulogic

Port

Clock_PHI2 System clock signal

signal_1_PC

signal_1_PC in std_ulogic

Port

Signal_1_PC Increment program counter

signal_ADL_PCL

signal_ADL_PCL in std_ulogic

Port

Signal_ADL_PCL Load PCL from address low bus

signal_PCL_ADL

signal_PCL_ADL in std_ulogic

Port

Signal_PCL_ADL Program counter low value to address low bus

signal_PCL_DB

signal_PCL_DB in std_ulogic

Port

Signal_PCL_DB Program counter low value to data bus

signal_PCL_PCL

signal_PCL_PCL in std_ulogic

Port

Signal_PCL_PCL Store program counter low value

signal_PCLC

signal_PCLC out std_ulogic

Port

Signal_PCLC Program counter low carry output

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/datapath/program_counter_low.vhdl