blinky.rtl Architecture Reference

Architecture >> blinky::rtl

Processes
PROCESS_0	( output_clk )
PROCESS_1	( number )

Components
clock_divider	<Entity clock_divider>

Signals
number	unsigned ( 0 to 7 ) := ( others = > ' 0 ' )
output_clk	std_ulogic := ' 0 '

Instantiations
divider	clock_divider <Entity clock_divider>

Member Function/Procedure/Process Documentation

PROCESS_0()

PROCESS_0

(

output_clk

)

PROCESS_1()

PROCESS_1 (   number   )

Process

Member Data Documentation

clock_divider

clock_divider

Component

divider

divider clock_divider

Instantiation

number

number unsigned ( 0 to 7 ) := ( others = > ' 0 ' )

Signal

output_clk

output_clk std_ulogic := ' 0 '

Signal

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The documentation for this design unit was generated from the following file:

• cores/blinky/core.vhdl