phased_clock_generator Entity Reference

Inheritance diagram for phased_clock_generator:

Ports
clk_in	in	std_ulogic
clk_out	out	std_ulogic
clk_phi1	out	std_ulogic
clk_phi2	out	std_ulogic

Detailed Description

A simple clock generator that generates two mutually independent clock signals from a single input clock signal.

Member Data Documentation

clk_in

clk_in in std_ulogic

Port

clk_out

clk_out out std_ulogic

Port

clk_phi1

clk_phi1 out std_ulogic

Port

clk_phi2

clk_phi2 out std_ulogic

Port

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The documentation for this design unit was generated from the following file:

• cores/phased_clock_generator/core.vhdl