Pass MOSFET entity that connects or isolates two 8-bit buses.
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|
enable | in | std_ulogic |
| | Control_Enable Enable signal that connects the buses when asserted
|
bus_1 | inout | std_ulogic_vector ( 7 downto 0 ) |
| | Data_Bus_1 First 8-bit bus
|
bus_2 | inout | std_ulogic_vector ( 7 downto 0 ) |
| | Data_Bus_2 Second 8-bit bus
|
Pass MOSFET entity that connects or isolates two 8-bit buses.
◆ bus_1
bus_1 inout std_ulogic_vector ( 7 downto 0 ) |
|
Port |
Data_Bus_1 First 8-bit bus
◆ bus_2
bus_2 inout std_ulogic_vector ( 7 downto 0 ) |
|
Port |
Data_Bus_2 Second 8-bit bus
◆ enable
Control_Enable Enable signal that connects the buses when asserted
The documentation for this design unit was generated from the following file: