mos_6502 Entity Reference

Ports
clock	in	std_ulogic
phi1	in	std_ulogic
phi2	in	std_ulogic
address	out	std_ulogic_vector ( 15 downto 0 )
data	inout	std_ulogic_vector ( 7 downto 0 )
superclock	in	std_ulogic

Member Data Documentation

address

address out std_ulogic_vector ( 15 downto 0 )

Port

clock

clock in std_ulogic

Port

data

data inout std_ulogic_vector ( 7 downto 0 )

Port

phi1

phi1 in std_ulogic

Port

phi2

phi2 in std_ulogic

Port

superclock

superclock in std_ulogic

Port

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The documentation for this design unit was generated from the following file:

• cores/ricoh_2A03/core.vhdl