blinky Entity Reference

Inheritance diagram for blinky:

Generics
divide_by	natural := 25

Ports
clk	in	std_ulogic := ' 0 '
led	out	std_ulogic_vector ( 0 to 7 ) := ( others = > ' 0 ' )

Detailed Description

A simple test module to assure toolchain functionality while I bootstrap the rest of the project

Member Data Documentation

clk

clk in std_ulogic := ' 0 '

Port

divide_by

divide_by natural := 25

Generic

led

led out std_ulogic_vector ( 0 to 7 ) := ( others = > ' 0 ' )

Port

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The documentation for this design unit was generated from the following file:

• cores/blinky/core.vhdl