nesgate
VHDL emulation of the Nintendo Entertainment System
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Processes
|
Signals
accumulator.rtl Architecture Reference
Architecture >>
accumulator::rtl
Processes
PROCESS_7
(
load_SB_AC
,
databus_SB
)
Signals
register_data
std_ulogic_vector
(
7
downto
0
)
:
=
(
others
=
>
'
0
'
)
Member Function/Procedure/Process Documentation
◆
PROCESS_7()
PROCESS_7
(
load_SB_AC
,
databus_SB
)
Process
Member Data Documentation
◆
register_data
register_data
std_ulogic_vector
(
7
downto
0
)
:
=
(
others
=
>
'
0
'
)
Signal
The documentation for this design unit was generated from the following file:
cores/ricoh_2A03/datapath/
accumulator.vhdl
accumulator
rtl
Generated by
1.9.8